EP610 Datasheet (Altera)

EP610, EPLD

The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration.

Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.

Classic devices support 100% TTL emulation and can easily integrate multiple

EP610 Features

* Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 t