AS4C4M32S - 4M x 32 bit Synchronous DRAM

Description

Table 1.

CLK Input Clock: CLK is driven by the system clock.

All SDRAM input signals are sampled on the positive edge of CLK.

Features

• Fast access time from clock: 5.4/5.4 ns.
• Fast clock rate: 166/143 MHz.
• Fully synchronous operation.
• Internal pipelined architecture.
• Four internal banks (1M x 32-bit x 4bank).
• Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleaved - Burst-Read-Single-Write.
• Burst stop function.
• Individual byte controlled by DQM0-3.
• Auto Refresh and Self Refresh.
• Operating temperature range - Commer.