TAAD08JU2

The TAAD08JU2 is T1/E1/J1 ATM Processor designed by Agere Systems.

Product Overview

Agere Systems

Datasheet Details

Part number	TAAD08JU2
Manufacturer	Agere Systems
File Size	2.28 MB
Description	T1/E1/J1 ATM Processor
Datasheet	TAAD08JU2_AgereSystems.pdf
Additional preview pages of the TAAD08JU2 datasheet.

Product details

Description

11 Pin Definitions 12 Pin Description 12 Package Pin Layout 21 Block Diagram 27 Software Components 28 9.1 Firmware29 9.2 Device Manager29 9.3 Setup File Utility (SFU) 30 9.4 TAAD08JU2 Application Code31 9.5 System Software32 9.6 Software Development Environment 32 9.7 Notes 33 Functional Overview34 10.1 Receive Direction Data Flow 34 10.1.1 PHY Layer 34 10.1.2 Low-Speed PHY Links 34 10.1.3 High-Speed PHY Links 35 10.1.4 TC and IMA Layers35 10.1.5 ATM Layer 36 10.1.6 AAL Engine36 10.1.7 Embedde

Features

s s System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC).

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Published: Feb 9, 2008 |