Description
A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM .
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
Features
* Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
* Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
* Signal +2.5V ± 5% power supply
* Individual Byte Write control capability
* Clock enable ( CEN) pin to enabl
Applications
* Three separate chip enables allow wide range of
options for CE control, address pipelining
* Internally self-timed write cycle
* Selectable BURST mode (Linear or Interleaved)
* SLEEP mode (ZZ pin) provided
* Available in 100 pin LQFP package
* Indus
