N9H30F51IEC
Description
The N9H30 series targeted for general purpose 32-bit microcontroller embeds an outstanding CPU core ARM926EJ-S, runs up to 300 MHz, with 16 KB I-cache, 16 KB D-cache and MMU, 56KB embedded SRAM and 16 KB IBR (Internal Boot ROM) for booting from USB, NAND and SPI FLASH. The N9H30 series integrates USB 2.0 HS HOST/Device controller with HS transceiver embedded, TFT type LCD controller, 2D graphics engine, I2S I/F controller, SD/MMC/NAND FLASH controller, GDMA and 8 channels 12-bit ADC controller with resistance touch screen functionality.
Key Features
- 1 Features
- Core - ARM® ARM926EJ-S™ processor core runs up to 300 MHz - Support 16 KB instruction cache and 16 KB data cache - Support MMU - Support JTAG Debug interface
- DDR SDRAM Controller - Support LVDDR and DDR2 SDRAM - Clock speed up to 150 MHz - Support 16-bit data bus width - Memory size depended on embedded SDRAM configuration by different part number.
- Embedded SRAM and ROM - Support 56K bytes embedded SRAM - Support 16K bytes Internal Boot ROM (IBR) - Support up to four booting modes - Boot from USB - Boot from eMMC - Boot from NAND Flash - Boot from SPI Flash
- Clock Control - Support two PLLs, up to 500 MHz, for high performance system operation - External 12 MHz high speed crystal input for precise timing operation - External 32.768 kHz low speed crystal input for RTC function and low speed clock source
- Ethernet MAC Controller - Support up to 2 Ethernet MAC controllers - Support IEEE Std. 802.3 CSMA/CD protocol - Support packet time stamping for IEEE Std. 1588 protocol - Support 10 and 100 Mbps operations - Support Half- and Full-duplex operations - Support RMII interface to Ethernet physical layer PHY - Support Ethernet physical layer PHY management through MDC and MDIO interface - Support flow control in Full-duplex mode to receive, recognize and transmit PAUSE frame - Support CAM-like function to recognize 48-bit Ethernet MAC address - Support Wake-On-LAN by detecting Magic Packet - Support 256 bytes transmit FIFO and 256 bytes receive FIFO - Support DMA function - Support internal loop back mode for diagnostic
- USB 2.0 Controller - Support USB Revision 2.0 specification - Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver - Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver - Support Control, Bulk, Interrupt, Isochronous and Split transfers - Support USB host function compliant to Enhanced Host Controller Interface (EHCI) 1.0
