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HEF4520BT - Dual binary counter

Download the HEF4520BT datasheet PDF. This datasheet also covers the HEF4520B variant, as both devices belong to the same dual binary counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR).

Key Features

  • Tolerant of slow clock rise and fall times.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HEF4520B-nexperia.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Nexperia

Part Number Description
HEF4520B Dual binary counter
HEF4520B-Q100 Dual binary counter
HEF4521B 24-stage frequency divider and oscillator
HEF4528-Q100B Dual monostable multivibrator
HEF4528B Dual monostable multivibrator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HEF4520B Dual binary counter Rev. 9 — 19 August 2024 Product data sheet 1. General description The HEF4520B is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2.