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74VHCT125 - Quad buffer/line driver

Download the 74VHCT125 datasheet PDF. This datasheet also covers the 74VHC125 variant, as both devices belong to the same quad buffer/line driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard JESD7-A.

The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs.

Key Features

  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accepts voltages higher than VCC.
  • Input levels:.
  • The 74VHC125 operates with CMOS logic levels.
  • The 74VHCT125 operates with TTL logic levels.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • CDM JESD22-C101C exceeds 1000 V.
  • Multiple package options.
  • Specified from -40 °C to +85 °C.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74VHC125-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74VHCT125 Quad buffer/line driver NXP
74VHCT125A QUAD BUS BUFFERS STMicroelectronics
74VHCT126 Quad buffer/line driver NXP
74VHCT126A QUAD BUS BUFFERS STMicroelectronics
74VHCT132A QUAD 2-INPUT SCHMITT NAND GATE STMicroelectronics

Other Datasheets by Nexperia

Part Number Description
74VHCT126 Quad buffer/line driver
74VHCT126-Q100 Quad buffer/line driver
74VHCT14 Hex inverting Schmitt trigger
74VHCT02 Quad 2-input NOR gate
74VHCT02-Q100 Quad 2-input NOR gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 3 — 8 April 2020 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2.