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74LVCH162373A - 16-bit D-type transparent latch

Download the 74LVCH162373A datasheet PDF. This datasheet also covers the 74LVC162373A variant, as both devices belong to the same 16-bit d-type transparent latch family and are provided as variant models within a single manufacturer datasheet.

Description

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω termination resistors and 3-state outputs.

The 74LVCH162373A has separate D-type inputs with bus hold for each latch.

Both devices can be used as two 8-bit transparent latches or a single 16bit transparent latch.

Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Multibyte flow-through standard pinout architecture.
  • Multiple low inductance supply pins for minimum noise and ground bounce.
  • Direct interface with TTL levels.
  • All data inputs have bus hold (74LVCH162373A only).
  • IOFF circuitry provides partial Power-down mode operation.
  • Complies with JEDEC standard:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LVC162373A-nexperia.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC162373A; 74LVCH162373A 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state Rev. 6 — 16 September 2021 Product data sheet 1. General description The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes.
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