Datasheet4U Logo Datasheet4U.com

74LVC74A - Dual D-type flip-flop

Datasheet Summary

Description

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input.

Features

  • 5 V tolerant inputs for interlacing with 5 V logic.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000.

📥 Download Datasheet

Datasheet preview – 74LVC74A

Datasheet Details

Part number 74LVC74A
Manufacturer nexperia
File Size 280.46 KB
Description Dual D-type flip-flop
Datasheet download datasheet 74LVC74A Datasheet
Additional preview pages of the 74LVC74A datasheet.

📁 Similar Datasheet

  • 74LVC74A - Dual D-type flip-flop (NXP)
  • 74LVC00A - LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE (STMicroelectronics)
  • 74LVC00A - QUADRUPLE 2-INPUT NAND GATES (Diodes)
  • 74LVC00A - Low-Voltage CMOS Quad 2-Input NAND Gate (ON Semiconductor)
  • 74LVC02 - Quad 2-input NOR gate (Philips)
  • 74LVC02A - Low-Voltage CMOS Quad 2-Input NOR Gate (ON Semiconductor)
  • 74LVC04A - HEX BUFFERS (Diodes)
  • 74LVC04A - Low-Voltage CMOS Hex Inverter (ON Semiconductor)
  • 74LVC04A - LOW VOLTAGE CMOS HEX INVERTER (STMicroelectronics)
  • 74LVC06A - HEX INVERTERS (Diodes)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 12 — 6 May 2025 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2.
Published: |