Datasheet4U Logo Datasheet4U.com

74LVC573A - Octal D-type transparent latch

General Description

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs.

Key Features

  • Wide supply voltage range from 1.2 to 3.6 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • IOFF circuitry provides partial Power-down mode operation.
  • High-impedance when VCC = 0 V.
  • Flow-through pinout architecture.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ES.

📥 Download Datasheet

Datasheet Details

Part number 74LVC573A
Manufacturer Nexperia
File Size 269.46 KB
Description Octal D-type transparent latch
Datasheet download datasheet 74LVC573A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVC573A Octal D-type transparent latch NXP
74LVC573A OCTAL D-TYPE LATCH STMicroelectronics
74LVC573A OCTAL TRANSPARENT D-TYPE LATCH Diodes
74LVC573A Low-Voltage CMOS Octal Transparent Latch ON Semiconductor
74LVC574A Octal D-type flip-flop NXP

Other Datasheets by Nexperia

Part Number Description
74LVC573A-Q100 Octal D-type transparent latch
74LVC574A Octal D-type flip-flop
74LVC541A Octal buffer/line driver
74LVC541A-Q100 Octal buffer/line driver
74LVC594A 8-bit shift register

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 8 — 27 August 2021 Product data sheet 1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices.