74LV4060-Q100 Datasheet | Nexperia

14-stage binary ripple counter with oscillator Rev. 2 - 24 March 2021 Product data sheet 1. General description The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - Wide supply voltage range from 1.0 V to 5.5 V - Optimized for low voltage applications from 1.0 V to 3.6 V - CMOS low power dissipation - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V - Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 °C - Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 °C - All active ponents on chip - RC or crystal oscillator configuration - plies with JEDEC standard no. 7A - ESD protection: - MIL-STD-883, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 Ω) 3. Applications - Control counters - Timers - Frequency dividers - Time-delay circuits Nexperia...