74LV138D Overview
Description
The 74LV138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The 74LVC138A features three enable inputs (Y1, Y2 and E3).
Key Features
- Wide supply voltage range from 1.0 to 5.5 V
- Optimized for low voltage applications: 1.0 V to 3.6 V
- CMOS low power dissipation
- Direct interface with TTL levels
- Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
- Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
- Demultiplexing capability
- Multiple input enable for easy expansion
- Ideal for memory chip select decoding
- Active LOW mutually exclusive outputs
