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74HCT74 - Dual D-type flip-flop

Download the 74HCT74 datasheet PDF. This datasheet also covers the 74HC74 variant, as both devices belong to the same dual d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop.

They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs.

Key Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Input levels:.
  • For 74HC74: CMOS level.
  • For 74HCT74: TTL level.
  • Symmetrical output impedance.
  • High noise immunity.
  • Balanced propagation delays.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC74-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HCT74
Manufacturer Nexperia
File Size 294.36 KB
Description Dual D-type flip-flop
Datasheet download datasheet 74HCT74 Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HCT74-Q100 Dual D-type flip-flop
74HCT74D Dual D-type flip-flop
74HCT7540 Octal Schmitt trigger buffer/line driver
74HCT7540D Octal Schmitt trigger buffer/line driver
74HCT7541 Octal Schmitt trigger buffer/line driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 8 — 9 February 2023 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.