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74HCT595-Q100 - serial or parallel-out shift register

This page provides the datasheet information for the 74HCT595-Q100, a member of the 74HC595-Q100 serial or parallel-out shift register family.

Datasheet Summary

Description

The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • 8-bit serial input.
  • 8-bit serial or parallel output.
  • Storage register with 3-state outputs.
  • Shift register with direct clear.
  • 100 MHz (typical) shift out frequency.
  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC595-Q100: CMOS level.
  • For 74HCT595-Q100: TT.

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Datasheet preview – 74HCT595-Q100

Datasheet Details

Part number 74HCT595-Q100
Manufacturer nexperia
File Size 295.51 KB
Description serial or parallel-out shift register
Datasheet download datasheet 74HCT595-Q100 Datasheet
Additional preview pages of the 74HCT595-Q100 datasheet.

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Full PDF Text Transcription

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74HC595-Q100; 74HCT595-Q100 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 4 — 11 March 2020 Product data sheet 1. General description The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
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