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74HCT594-Q100 - 8-bit shift register

Download the 74HCT594-Q100 datasheet PDF. This datasheet also covers the 74HC594-Q100 variant, as both devices belong to the same 8-bit shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • Synchronous serial input and output.
  • Complies with JEDEC standard No.7A.
  • 8-bit parallel output.
  • Shift and storage registers have independent direct clear and clocks.
  • Independent clocks for shift and storage registers.
  • 100 MHz (typical).
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC594-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Nexperia

Part Number Description
74HCT594 8-bit shift register
74HCT594D 8-bit shift register
74HCT595 serial or parallel-out shift register
74HCT595-Q100 serial or parallel-out shift register
74HCT595BQ serial or parallel-out shift register

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC594-Q100; 74HCT594-Q100 8-bit shift register with output register Rev. 2 — 13 June 2016 Product data sheet 1. General description The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If both clocks are connected together, the shift register is always one count pulse ahead of the storage register.