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74HCT1G126 - Bus buffer/line driver

Download the 74HCT1G126 datasheet PDF. This datasheet also covers the 74HC1G126 variant, as both devices belong to the same bus buffer/line driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC1G126; 74HCT1G126 is a single buffer/line driver with 3-state output.

Inputs include clamp diodes.

This enables the use of current limitng resistors to interface inputs to voltages in excess of VCC.

Key Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • Symmetrical output impedance.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Balanced propagation delays.
  • Input levels:.
  • For 74HC1G126: CMOS level.
  • For 74HCT1G126: TTL level.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD protec.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC1G126-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Nexperia

Part Number Description
74HCT1G125 Bus buffer/line driver
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74HCT1G14 Inverting Schmitt trigger
74HCT1G14-Q100 Inverting Schmitt trigger
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC1G126; 74HCT1G126 Bus buffer/line driver; 3-state Rev. 5 — 17 January 2022 Product data sheet 1. General description The 74HC1G126; 74HCT1G126 is a single buffer/line driver with 3-state output. Inputs include clamp diodes. This enables the use of current limitng resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • Symmetrical output impedance • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Balanced propagation delays • Input levels: • For 74HC1G126: CMOS level • For 74HCT1G126: TTL level • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.