74HC4024 datasheet, counter equivalent, nexperia

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datasheet Download (Size : 207.82KB)

Features and benefits

* Low-power dissipation
* Complies with JEDEC standard no. 7A
* CMOS input levels
* ESD protection:
* HBM JESD22-A114F exceeds 2 000 V
* MM JESD22.

Description

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR c.

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