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74HC40105D - 4-bit x 16-word FIFO register

Download the 74HC40105D datasheet PDF. This datasheet also covers the 74HC40105 variant, as both devices belong to the same 4-bit x 16-word fifo register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words.

It can handle input and output data at different shifting rates.

This feature makes it particularly useful as a buffer between asynchronous systems.

Key Features

  • Independent asynchronous inputs and outputs.
  • Expandable in either direction.
  • Reset capability.
  • Status indicators on inputs and outputs.
  • 3-state outputs.
  • CMOS input levels.
  • Complies with JEDEC standard JESD7A.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Order.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC40105-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC40105D
Manufacturer Nexperia
File Size 310.10 KB
Description 4-bit x 16-word FIFO register
Datasheet download datasheet 74HC40105D Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC40105 4-bit x 16-word FIFO register Rev. 5 — 19 April 2019 Product data sheet 1. General description The 74HC40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop.