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74HC160D - Presettable synchronous BCD decade counter

Download the 74HC160D datasheet PDF. This datasheet also covers the 74HC160 variant, as both devices belong to the same presettable synchronous bcd decade counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry.

Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW.

Key Features

  • Complies with JEDEC standard no. 7A.
  • CMOS input levels.
  • Synchronous counting and loading.
  • 2 count enable inputs for n-bit cascading.
  • Asynchronous reset.
  • Positive-edge triggered clock.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature r.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC160-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC160D
Manufacturer Nexperia
File Size 245.26 KB
Description Presettable synchronous BCD decade counter
Datasheet download datasheet 74HC160D Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC160 Presettable synchronous BCD decade counter; asynchronous reset Rev. 4 — 27 March 2019 Product data sheet 1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).