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74HC139 - Dual 2-to-4 line decoder/demultiplexer

General Description

The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3).

Key Features

  • Input levels:.
  • For 74HC139: CMOS level.
  • For 74HCT139: TTL level.
  • Demultiplexing capability.
  • 2 independent 2-to-4 decoders.
  • Multifunction capability.
  • Suitable for memory decoding, data routing or code conversion.
  • Complies with JEDEC standard no. 7A.
  • Active LOW mutually exclusive outputs.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Sp.

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Datasheet Details

Part number 74HC139
Manufacturer Nexperia
File Size 238.51 KB
Description Dual 2-to-4 line decoder/demultiplexer
Datasheet download datasheet 74HC139 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74HC139; 74HCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 5 — 14 January 2021 Product data sheet 1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.