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74AVC16374-Q100 - 16-bit edge triggered D-type flip-flop

Description

The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

The 74AVC16374-Q100 consist of 2 sections of 8 edge-triggered flip-flops.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 3).
  • Specified from 40 C to +85 C.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • Complies with JEDEC standards:.
  • JESD8-7 (1.2 V to 1.95 V).
  • JESD8-5 (1.8 V to 2.7 V).
  • JESD8-1A (2.7 V to 3.6 V).
  • ESD protection:.
  • MIL-STD-883, method 3015 exceeds 1000 V.
  • HBM JESD22-A114F exceeds 1000 V.
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ).
  • CMOS low power consumption.

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Datasheet preview – 74AVC16374-Q100

Datasheet Details

Part number 74AVC16374-Q100
Manufacturer nexperia
File Size 766.95 KB
Description 16-bit edge triggered D-type flip-flop
Datasheet download datasheet 74AVC16374-Q100 Datasheet
Additional preview pages of the 74AVC16374-Q100 datasheet.

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Full PDF Text Transcription

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74AVC16374-Q100 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state Rev. 2 — 16 March 2015 Product data sheet 1. General description The 74AVC16374-Q100 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374-Q100 consist of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section. The 74AVC16374-Q100 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion).
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