74AUP2G97 Datasheet | Nexperia

description The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits - Wide supply voltage range from 0.8 V to 3.6 V - High noise immunity - ESD protection: - HBM JESD22-A114F exceeds 5000 V - MM JESD22-A115-A exceeds 200 V - CDM JESD22-C101E exceeds 1000 V - Low static power consumption; ICC = 0.9 μA (maximum) - Latch-up performance exceeds 100 m A per JESD 78 Class II - Inputs accept voltages up to 3.6 V - Low noise overshoot and undershoot < 10 % of VCC - IOFF circuitry provides partial power-down mode operation - Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP2G97DP -40 °C to +125 °C 74AUP2G97GU -40 °C to +125 °C Name TSSOP10 XQFN10 Description Version plastic thin shrink small outline package; 10 leads; SOT552-1 body width 3 mm plastic, extremely thin quad flat package; no leads; SOT1160-1 10 terminals; body 1.40 × 1.80 × 0.50 mm Nexperia Low-power dual PCB configurable multiple function gate 4. Marking Table 2. Marking Type number 74AUP2G97DP 74AUP2G97GU Marking code [1] a V a V [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram n A n B n C Fig. 1. Logic symbol (one gate) n Y aaa-015396 6. Pinning information 6.1. Pinning 1A 1 1B 2 1C 3 2Y 4 GND 5 10 VCC 9 1Y 8 2C 7...