74AUP2G80 flip-flop equivalent, low-power dual d-type flip-flop.
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
* JESD8-12 (0.8 V to 1.3 V)
* JESD8-11 (0.9 V t.
using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is.
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to.
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