74AUP2G240
description
The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (n OE). A HIGH level at pin n OE causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This device has the input-disable feature
, which allows floating input signals. The inputs are disabled when the output enable input n OE is HIGH.
2. Features and benefits
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- plies with JEDEC standards:
- JESD8-12 (0.8...
