Datasheet Details
| Part number | 74AUP1G132 |
|---|---|
| Manufacturer | Nexperia |
| File Size | 281.43 KB |
| Description | Low-power 2-input NAND Schmitt trigger |
| Datasheet |
 74AUP1G132 Datasheet
|
|
|
General Description
The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
Key Features
- Wide supply voltage range from 0.8 V to 3.6 V.
- CMOS low power dissipation.
- High noise immunity.
- Overvoltage tolerant inputs to 3.6 V.
- Low static power consumption; ICC = 0.9 μA (maximum).
- Latch-up performance exceeds 100 mA per JESD 78 Class II.
- Low noise overshoot and undershoot < 10 % of VCC.
- IOFF circuitry provides partial Power-down mode operation.
- Complies with JEDEC standards:.
- JESD8-12 (0.8 V to 1.3.