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74AUP1G07 - Low-power buffer

Description

The 74AUP1G07 is a single buffer with open-drain output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • High noise immunity.
  • CMOS low power dissipation.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP1G07 Low-power buffer with open-drain output Rev. 10 — 13 January 2022 Product data sheet 1. General description The 74AUP1G07 is a single buffer with open-drain output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • CMOS low power dissipation • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.
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