74ALVCH16825DGG Datasheet | Nexperia

description The 74ALVCH16825 is an 18- bit non-inverting buffer/driver with 3-state outputs for bus-oriented applications. The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding n Yn outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state. The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits - Wide supply voltage range of 1.2V to 3.6V - CMOS low power consumption - Multi Byte flow-through standard pin-out architecture - Low inductance multiple VCC and GND pins for minimum noise and ground bounce - Direct interface with TTL levels (2.7 V to 3.6 V) - Bus hold on data inputs - Output drive capability 50 Ω transmission lines at 85 °C - Current drive ±24 m A at 3.0 V - plies with JEDEC standards: - JESD8-5 (2.3 V to 2.7 V) - JESD8B/JESD36 (2.7 V to 3.6 V) - ESD protection: - HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V - CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description - 40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm Version SOT364-1 Nexperia 74ALVCH16825 18-bit buffer/driver; 3-state 4 Functional diagram 55 54 52 51 49 48 47 45 44 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1 1OE1 56 1OE2 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2 3 5 6 8 9 10 12 13 41 40 38 37 36 34 33 31 30 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 28 2OE1 29 2OE2 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 15 17 19...