Datasheet Summary
18-bit universal bus transceiver; 3-state
Rev. 3
- 13 August 2018
Product data sheet
1. General description
The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus patible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW,...
