Datasheet4U Logo Datasheet4U.com

74ALVCH16374 - 16-bit edge-triggered D-type flip-flop

Description

The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs.

The device can be used as two 8-bit flip-flops or one 16-bit flip-flop.

Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • Complies with JEDEC standards:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).
  • CMOS low power dissipation.

📥 Download Datasheet

Datasheet preview – 74ALVCH16374

Datasheet Details

Part number 74ALVCH16374
Manufacturer nexperia
File Size 227.44 KB
Description 16-bit edge-triggered D-type flip-flop
Datasheet download datasheet 74ALVCH16374 Datasheet
Additional preview pages of the 74ALVCH16374 datasheet.

📁 Similar Datasheet

  • 74ALVCH16374 - LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (STMicroelectronics)
  • 74ALVCH16374 - 16-bit edge-triggered D-type flip-flop (NXP)
  • 74ALVCH16374 - Low Voltage 16-Bit D-Type Flip-Flop (Fairchild Semiconductor)
  • 74ALVCH16374 - Low-Voltage 16-Bit D-Type Flip-Flop (ON Semiconductor)
  • 74ALVCH16373 - 2.5V/3.3V 16-bit D-type transparent latch (NXP)
  • 74ALVCH16373 - Low Voltage 16-Bit Transparent Latch (Fairchild Semiconductor)
  • 74ALVCH162240 - Low Voltage 16-Bit Inverting Buffer/Line Driver (Fairchild Semiconductor)
  • 74ALVCH162244 - 16-bit buffer/line driver (NXP)
  • 74ALVCH162244 - Low Voltage 16-Bit Buffer/Line Driver (Fairchild Semiconductor)
  • 74ALVCH162244 - 3.3V CMOS 16-BIT BUFFER/DRIVER (Renesas)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74ALVCH16374 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 7 — 23 November 2021 Product data sheet 1. General description The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops.
Published: |