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74ALVC573 - Octal D-type transparent latch

Description

The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications.

A latch enable (LE) input and an outputs enable (OE) input are common to all latches.

Features

  • Wide supply voltage range from 1.65 V to 3.6 V.
  • 3.6 V tolerant inputs/outputs.
  • CMOS low power consumption.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Power-down mode.
  • Latch-up performance exceeds 250 mA.
  • Complies with JEDEC standards:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22.

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Datasheet preview – 74ALVC573

Datasheet Details

Part number 74ALVC573
Manufacturer nexperia
File Size 263.65 KB
Description Octal D-type transparent latch
Datasheet download datasheet 74ALVC573 Datasheet
Additional preview pages of the 74ALVC573 datasheet.

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Full PDF Text Transcription

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74ALVC573 Octal D-type transparent latch; 3-state Rev. 4 — 30 April 2021 Product data sheet 1. General description The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE.
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