I Balanced propagation delays I All inputs have a Schmitt-trigger action I 3-state non-inverting outputs for bus orientated applications I 8-bit positive, edge-triggered .

A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their i.

The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D.

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