TSB81BA3E Datasheet | Texas Instruments

Features - 1 Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit Signaling Rates - Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standard for High Performance Serial Bus - Fully Interoperable With Firewire, i.LINK, and SB1394™, Implementation of IEEE Std 1394 - Provides Three Fully Backward patible, (1394a-2000 Fully pliant) Bilingual P1394b Cable Ports at up to 800 Megabits per Second (Mbits/s) - Provides Three 1394a-2000 Fully pliant Cable Ports at 100/200/400 Mbits/s - Full 1394a-2000 Support Includes: - Connection Debounce - Arbitrated Short Reset - Multispeed Concatenation - Arbitration Acceleration - Fly-By Concatenation - Port Disable/Suspend/Resume - Extended Resume Signaling for patibility With Legacy DV Devices - Power-Down Features to Conserve Energy in Battery Powered Applications - Low-Power Sleep Mode - Fully pliant With Open Host Controller Interface (HCI) Requirements - Cable Power Presence Monitoring - Cable Ports Monitor Line Conditions for Active Connection to Remote Node - Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a-2000 Features - Data Interface to Link-Layer Controller Pin Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz) - Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation - Interoperable With Link-Layer Controllers Using 3.3-V Supplies - Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies - Low Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz - Separate Bias (TPBIAS) for Each Port - Low Cost, High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package and 168-Pin ZAJ (BGA) Package - Software Device Reset (SWR) - Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the...