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TPIC5203 - power DMOS array

Description

NC

independent electrically isolated N-channel enhancement-mode DMOS transistors.

Features

  • integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC5203 is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature range of.
  • 40°C to 125°C. schematic DRAIN1 8 GATE2 3.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ą TPIC5203 2ĆCHANNEL INDEPENDENT GATEĆPROTECTED POWER DMOS ARRAY SLIS040 − SEPTEMBER 1994 • Low rDS(on) . . . 0.26 Ω Typ • High Voltage Output . . . 60 V D PACKAGE (TOP VIEW) • Extended ESD Capability . . . 4000 V • Pulsed Current . . . 8 A Per Channel • Fast Commutation Speed GND SOURCE1 GATE2 1 2 3 8 DRAIN1 7 GATE1 6 SOURCE2 DRAIN2 4 5 NC description NC − No internal connection The TPIC5203 is a monolithic gate-protected power DMOS array that consists of two independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs.