Datasheet Summary
TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
D pare, Select, and Store Unit (CSSU) for the Add/pare Selection of the Viterbi Operator
D Exponent Encoder to pute an
Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary...