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TMS320C30 - DIGITAL SIGNAL PROCESSORS

Description

SPRS032A APRIL 1996 REVISED JUNE 1997 D Two 32-Bit External Ports D 24- and 13-Bit Addresses D 0.7-µm Enhanced Performance Implanted CMOS (EPIC™) Technology D 208-Pin Plastic Quad Flat Package ( PPM Suffix ) D 181-Pin Grid Array Ceramic Package (GEL Suffix) D Eight Extended-Prec

Features

  • General-purpose.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TMS320C30 DIGITAL SIGNAL PROCESSOR D High-Performance Floating-Point Digital Signal Processor (DSP) – TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C30-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320C30-33 (5 V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS – TMS320C30-27 (5 V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.
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