SN74LS165A
Description
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.
Key Features
- gated clock (CLK) inputs and plementary outputs from the eighth bit
- All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design
- Clocking is acplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function
- Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input
- Clock inhibit (CLK INH) should be changed to the high level only while CLK is high
- Parallel loading is inhibited as long as SH/LD is high
- SN54165, SN54LS165A
- J OR W PACKAGE SN74165
- N PACKAGE SN74LS165A
- D, N, OR NS PACKAGE (TOP VIEW) SH/LD CLK E F G H QH GND 1 2 3 4 5 6 7 8 16 VCC 15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH SN54LS165A
