gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes are.

D Low Input Current of 1 µA Max D ESD Protection Exceeds 2000 V Per D Synchronous Load MIL-STD-883, Method 3015; Exc.

ordering information This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or C D CLK INH CLK GND 4 5 6 7 8 13 QH 12 G 11 F 10 E 9 CLR serial-in modes ar.

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