SN74AUP1G02 datasheet, gate equivalent, Texas Instruments

Features and benefits

*1 Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
* Low Static-Power Consumption (ICC = 0.9 μA Max)
* Low Dynamic-Power Consumption (Cp.

Application

* Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
* ESD Performance Tested Per JESD 22
.

Description

This single 2-input positive-NOR gate performs the Boolean function Y = A + B or Y = A × B in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm SOT (5) 1.60 mm .

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