Datasheet4U Logo Datasheet4U.com

SN74AUCH32374 - 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

Description

This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

📥 Download Datasheet

Datasheet preview – SN74AUCH32374

Datasheet Details

Part number SN74AUCH32374
Manufacturer Texas Instruments
File Size 281.21 KB
Description 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Datasheet download datasheet SN74AUCH32374 Datasheet
Additional preview pages of the SN74AUCH32374 datasheet.

📁 Similar Datasheet

  • SN74101 - AND-OR Gate (ETC)
  • SN74102 - AND Gate (ETC)
  • SN74103 - Dual J-K Flip-Flop (ETC)
  • SN74106 - Dual J-K Flip-Flop (ETC)
  • SN74108 - Dual J-K Flip Flop (ETC)
  • SN7411 - Triple 3-Input AND (ETC)
  • SN74120 - Dual Pulse Synchronizers / Drivers (Texas Instruments Inc)
  • SN74124 - Dual Voltage Controlled Oscillators (ETC)
  • SN7415 - Triple 3 Input AND Gate (Motorola)
  • SN74381 - integrated circuits (ETC)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
D Member of the Texas Instruments Widebus+ Family D Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation D Ioff Supports Partial-Power-Down Mode Operation D Sub 1-V Operable D Max tpd of 2.8 ns at 1.8 V D Low Power Consumption, 40-µA Max ICC SN74AUCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES476 – AUGUST 2003 D ±8-mA Output Drive at 1.8 V D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 32-bit edge-triggered D-type flip-flop is operational at 0.
Published: |