SN74ALS843 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS232A
DECEMBER 1983
REVISED JANUARY 1995
DW OR NT PACKAGE (TOP VIEW)
OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 9D 10 CLR 11 GND 12
24 VCC 23 1Q 22 2Q 21 3Q 20 4Q 19 5Q 18 6Q 17 7Q 16 8Q 15 9Q 14 PRE 13 LE
Features
3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The nine latches are transparent D-type latches with noninverting data (D) inputs. A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neit.
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• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout • Provides Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or Buses With Parity
• Buffered Control Inputs to Reduce
dc Loading Effects
• Power-Up High-Impedance State • Package Options Include Plastic
Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs
description
SN74ALS843 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS232A – DECEMBER 1983 – REVISED JANUARY 1995
DW OR NT PACKAGE (TOP VIEW)
OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 9D 10 CLR 11 GND 12
24 VCC 23 1Q 22 2Q 21 3Q 20 4Q 19 5Q 18 6Q 17 7Q 16 8Q 15 9Q 14 PRE 13 LE
This 9-bit bus-interface D-type latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedan
SN74ALS843 Datasheet
