SN65LVP17 datasheet, stage/buffers equivalent, Texas Instruments

Features and benefits

* Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
* Clock Rates to 2 GHz
– 140-ps Output Transition Times
– 0.11 ps Ty.

Application

* PECL-to-LVDS Translation
* Clock Signal Amplification DESCRIPTION These four devices are high-frequency oscil.

Description

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully diff.

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