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SN65DSI86-Q1 - MIPI DSI to eDP Bridge

General Description

The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge

Key Features

  • 1 Embedded DisplayPort™ (eDP™) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
  • Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00.
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5 Gbps Per Lane.
  • Supports 18 bpp and 24 bpp DSI Video Packets W.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN65DSI86-Q1 SLLSEJ5A – JULY 2014 – REVISED DECEMBER 2015 SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge 1 Features •1 Embedded DisplayPort™ (eDP™) 1.4 Compliant Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR), 2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2). • Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00 • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.