SN54ALS161B Datasheet | Texas Instruments

description These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The ’ALS161B, ’ALS163B, ’AS161, and ’AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . J PACKAGE SN74ALS161B, SN74AS161, SN74AS163 . . . D OR N PACKAGE SN74ALS163B . . . D, DB, OR N PACKAGE (TOP VIEW) CLR 1 CLK 2 A3 B4 C5 D6 ENP 7 GND 8 16 VCC 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . FK PACKAGE (TOP VIEW) CLK CLR NC VCC RCO 3 2 1 20 19 A4 18 QA B5 17 QB NC 6 16 NC C7 15 QC 9 10 11 12 13 ENP GND NC LOAD These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. - No internal connection The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse,...