Datasheet4U Logo Datasheet4U.com

SN54ABT162601 - 18-BIT UNIVERSAL BUS TRANSCEIVERS

Description

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SN54HC595J 16-bit bus transceiver and transparant D-type latch nexperia
SN54LS00 QUAD 2-INPUT NAND GATE Motorola Inc
SN54LS01 QUAD 2-INPUT NAND GATE Motorola Inc
SN54LS02 QUAD 2-INPUT NOR GATE Motorola Inc
SN54LS03 QUAD 2-INPUT NAND GATE Motorola Inc

Other Datasheets by Texas Instruments

Part Number Description
SN54ABT16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
SN54ABT162244 16-BIT BUFFERS/DRIVERS
SN54ABT162245 16-Bit BUS TRANSCEIVERS
SN54ABT16240A 16-BIT BUFFERS/DRIVERS
SN54ABT16241A 16-BIT BUFFERS/DRIVERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 D Members of the Texas Instruments Widebus ™ Family D B-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D UBT ™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode D Latch-Up Performance Exceeds 500 mA Per JESD 17 D Typical VOLP (Output Ground Bounce) < 0.