Datasheet Details
| Part number | SM320C50-EP |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 458.45 KB |
| Description | Digital Signal Processor |
| Datasheet |
 SM320C50-EP Datasheet
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| Part number | SM320C50-EP |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 458.45 KB |
| Description | Digital Signal Processor |
| Datasheet |
SM320C50-EP Datasheet
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The SM320C50-EP digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-µm double-level metal CMOS technology.
The C50 is the first DSP from TI designed as a fully static device.
Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.
SM320C50ĆEP DIGITAL SIGNAL PROCESSOR D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product Change Notification D Qualification Pedigree† D Military Operating Temperature Range: −55°C to 125°C D Industrial Operating Temperature Range: −40°C to 85°C D Fast Instruction Cycle Time (30 ns and 40 ns) and 25 ns for Industrial Temp Range D Source-Code Compatible With All TMS320C1x and TMS320C2x Devices D RAM-Based Operation − 9K × 16-Bit Single-Cycle On-Chip Program/Data RAM − 1056 × 16-Bit Dual-Access On-Chip Data RAM D 2K × 16-Bit On-Chip Boot ROM D 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) D 32-Bit Arithmetic Logic Unit (ALU) − 32-bit Accumulator (ACC) − 32-Bit Accumulator Buffer (ACCB) D 16-Bit Parallel Logic Unit (PLU) D 16 × 16-Bit Multiplier, 32-Bit Product D 11 Context-Switch Registers D Two Buffers for Circular Addressing SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 17 18 PQ PACKAGE (TOP VIEW) 1 132 117 116 50 84 51 83 D Full-Duplex Synchronous Serial Port D Time-Division Multiplexed Serial Port (TDM) D Timer With Control and Counter Registers D 16 Software-Programmable Wait-State Generators D Divide-by-One Clock Option D IEEE 1149.
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