*1 Minimum VDDQ:
  – 1.8 V (LP2996-N)
  – 1.35 V (LP2996A)
* Source and Sink Current
* Low Output Voltage Offset
* No External.

* LP2996-N: DDR1 and DDR2 Termination Voltage
* LP2996A: DDR1, DDR2, DDR3, and DDR3L Termination Voltage
* F.

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The de.

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