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LMK04828 - Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner

Download the LMK04828 datasheet PDF (LMK04821 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for ultra low-noise jesd204b compliant clock jitter cleaner.

Description

The LMK0482x family is the industry's highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks.

SYSREF can be provided using both DC and AC coupling.

Features

  • 1 JEDEC JESD204B Support.
  • Ultra-Low RMS Jitter.
  • 88 fs RMS Jitter (12 kHz to 20 MHz).
  • 91 fs RMS Jitter (100 Hz to 20 MHz).
  • 162.5 dBc/Hz Noise Floor at 245.76 MHz.
  • Up to 14 Differential Device Clocks from PLL2.
  • Up to 7 SYSREF Clocks.
  • Maximum Clock Output Frequency 3.1 GHz.
  • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2.
  • Up to 1 Buffered VCXO/Crystal Output from PLL1.
  • LVPECL, LVDS,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LMK04821-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments
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  • LMK04826 - Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
  • LMK04803 - Low-Noise Clock Jitter Cleaner
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Full PDF Text Transcription

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Product Folder Order Now Technical Documents Tools & Software Support & Community LMK04821, LMK04826, LMK04828 SNAS605AS – MARCH 2013 – REVISED MAY 2020 LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 1 Features •1 JEDEC JESD204B Support • Ultra-Low RMS Jitter – 88 fs RMS Jitter (12 kHz to 20 MHz) – 91 fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at 245.76 MHz • Up to 14 Differential Device Clocks from PLL2 – Up to 7 SYSREF Clocks – Maximum Clock Output Frequency 3.
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