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LMK04803, LMK04805, LMK04806, LMK04808
SNAS489K – MARCH 2011 – REVISED DECEMBER 2014
LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features
•1 Ultra-Low RMS Jitter Performance – 111 fs RMS Jitter (12 kHz to 20 MHz) – 123 fs RMS Jitter (100 Hz to 20 MHz)
• Dual Loop PLLatinum™ PLL Architecture • PLL1
– Integrated Low-Noise Crystal Oscillator Circuit – Holdover Mode when Input Clocks are Lost – Automatic or Manual Triggering/Recovery • PLL2 – Normalized PLL Noise Floor of –227 dBc/Hz – Phase Detector Rate up to 155 MHz – OSCin Frequency-Doubler – Integrated Low-Noise VCO • 2 Redundant Input Clocks with LOS – Automatic and Manual Switch-Over Modes • 50 % Duty Cycle Output Divides, 1 to 1