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LMK04131 - Family Clock Jitter Cleaner

Download the LMK04131 datasheet PDF (LMK04100 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for family clock jitter cleaner.

Description

The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules.

Features

  • 1.
  • 23 Cascaded PLLatinum™ PLL Architecture.
  • PLL1.
  • Redundant Reference Inputs.
  • Loss of Signal Detection.
  • Automatic and Manual Selection of Reference Clock Input.
  • PLL2.
  • Phase Detector Rate up to 100 MHz.
  • Input Frequency-Doubler.
  • Integrated VCO.
  • Outputs.
  • LVPECL/2VPECL, LVDS, and LVCMOS Formats.
  • Support Clock Rates up to 1080 MHz.
  • Five Dedicated Channel Divider Blocks.
  • Common.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LMK04100-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments
  • LMK04133 - Family Clock Jitter Cleaner
  • LMK04100 - Family Clock Jitter Cleaner
  • LMK04101 - Family Clock Jitter Cleaner
  • LMK04102 - Family Clock Jitter Cleaner
  • LMK04110 - Family Clock Jitter Cleaner
  • LMK04111 - Family Clock Jitter Cleaner
  • LMK04000 - Family Low-Noise Clock Jitter Cleaner
  • LMK04001 - Family Low-Noise Clock Jitter Cleaner

Full PDF Text Transcription

Click to expand full text
www.ti.com LMK04100, LMK04101, LMK04102, LMK04110 LMK04111, LMK04131, LMK04133 SNAS516B – APRIL 2011 – REVISED NOVEMBER 2012 LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs Check for Samples: LMK04100, LMK04101, LMK04102, LMK04110, LMK04111, LMK04131, LMK04133 FEATURES 1 •23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, LVDS, and LVCMOS Formats – Support Clock Rates up to 1080 MHz – Five Dedicated Channel Divider Blocks – Common Output Frequencies Supported: – 30.72 MHz, 61.44 MHz, 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz, 106.25 MHz, 125 MHz, 122.
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