LMK04110 Features
* 1
* 23 Cascaded PLLatinum™ PLL Architecture
* PLL1
* Redundant Reference Inputs
* Loss of Signal Detection
* Automatic and Manual Selection of Reference Clock Input
* PLL2
* Phase Detector Rate up to 100 MHz
* Input Frequency-Doubler
Datasheet Details
LMK04110, LMK04100
817.92 KB
Family clock jitter cleaner.
This datasheet PDF includes multiple part numbers: LMK04110, LMK04100.
Please refer to the document for exact specifications by model.
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LMK04110 Distributor
